Code	________
Year	2017
Instructor	Bertini (University of Florence)
Location	Florence
ECTS Credits	4

       

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Schedule

 

Day	Time	Room
24/01/2017	10:00–13:00	115 Santa Marta (Firenze)
25/01/2017	10:00–13:00	115 Santa Marta (Firenze)
26/01/2017	10:00–13:00	115 Santa Marta (Firenze)
27/01/2017	09:00–13:00	Lab. ex Forno - Santa Marta (Firenze)

       

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Abstract

 

• GPU architecture
  • comparison w.r.t CPU architecture

• SIMT

• What is CUDA
  • Hello World in CUDA

• CUDA Memory organization: introduction

• Threads organization and setup
  • Exercises:
    • summing vectors
    • matrix multiplication
• Grids, blocks and threads
  • thread scheduling
  • Threads and divergence

• Good practices in blocks and threads organization
  • 2D CUDA kernels
  • 3D CUDA kernels

• CUDA memory hierarchy
  • shared, device and constant memory

• Efficient CUDA programming
  • tiling: introduction
  • tiling: how to
  • synchronization barriers
  • phase-based processing
  • border checking

• Performance considerations
  • DRAM burst
  • memory coalescing
• atomic instructions
• privatization
• exercises:
  • histogram computation
  • ID convolution
    • how to use constant memory
    • tiling
  • 2D convolution
    • tiling
  • Tiling performance evaluation

 

• Lab activity: 2D convolution for image filtering
  • hanndling 2D borders
  • using constant memory for convolution weights
  • conditions for tiling and computation